Lenze EVS 9300 series - Page 479

Application examples
12.4 Master frequency bus - slave - drive (C0005 = 6000)
12-11
L
EDSVS9332S-K EN 3.0
Act. phase
Phase trimming
Phase trimming=f(n)
Set phase
Phase offset
Speed
trimming
F
I
X
E
D
0
D
I
G
I
N
1
F
I
X
E
D
0
F
I
X
E
D
0
%
F
I
X
E
D
1
0
0
%
C
0
4
7
4
/
1
Speed
limitation
Speed
controller
Torque
limitation
Actual speed
Phase controller
Current controller
C
0
4
2
5
D
F
I
N
C
0
4
7
2
/
5
C
0
0
3
2
C
0
4
7
3
/
1
C
0
4
7
3
/
3
C
I
N
H
O
R
1
1
Q
S
P
6
2
C
0
1
0
8
/
1
C
0
1
0
9
/
1
C
4
3
4
/
1
+
+
C
0
0
1
7
C
0
6
8
0
C
0
6
8
1
C
0
6
8
3
/
1
C
M
P
1
A
N
E
G
C
0
4
7
2
/
3
*
-
1
F
I
X
E
D
0
F
I
X
E
D
1
F
I
X
E
D
0
%
F
I
X
E
D
0
%
C
0
4
7
2
/
6
Q
S
P
T
R
I
P
-
S
E
T
T
R
I
P
-
R
E
S
E
T
F
I
X
E
D
0
N
A
C
T
=
0
T
R
I
P
R
D
Y
N
A
C
T
=
0
N
A
C
T
=
0
6
3
C
0
1
0
8
/
2
C
0
1
0
9
/
2
C
4
3
9
/
1
+
+
X
9
X
1
0
X
6
X
6
*
a
b
b
a
*
a
b
b
a
+
+
1
0
+
+
C
0
5
3
7
C
0
5
3
6
/
2
C
0
5
3
6
/
1
C
0
0
3
3
C
0
5
3
3
C
0
5
3
0
C
0
2
5
2
C
0
5
3
6
/
3
C
0
5
3
8
/
2
C
0
5
3
9
D
F
S
E
T
D
F
S
E
T
-
N
O
U
T
+
-
D
F
S
E
T
-
A
-
T
R
I
M
D
F
S
E
T
-
N
-
T
R
I
M
D
F
S
E
T
-
R
A
T
-
D
I
V
D
F
S
E
T
-
R
E
S
E
T
D
F
S
E
T
-
I
N
D
F
S
E
T
-
P
S
E
T
D
F
S
E
T
-
V
P
-
D
I
V
D
F
S
E
T
-
P
O
U
T
D
F
S
E
T
-
S
E
T
C
0
5
3
8
/
3
+
+
C
0
2
5
3
C
0
5
3
1
C
0
5
3
5
C
0
5
3
2
2
1
2
1
E
4
E
5
X
5
X
5
X
9
/
6
,
7
M
C
T
R
L
-
P
H
I
-
A
C
T
C
0
5
3
8
/
1
D
F
S
E
T
-
0
-
P
U
L
S
E
D
F
S
E
T
-
A
C
K
C
0
5
2
5
C
0
5
2
2
C
0
5
2
4
C
0
5
2
1
C
0
5
2
0
C
0
5
2
7
C
0
5
2
6
C
0
5
2
3
C
0
5
3
4
*
C
0
5
2
9
C
0
5
2
8
/
1
C
0
5
2
8
/
2
C
T
R
L
E
1
E
2
E
3
E
4
E
5
1
0
C
0
1
1
4
/
1
.
.
.
5
D
I
G
I
N
D
I
G
I
N
1
D
I
G
I
N
2
D
I
G
I
N
3
D
I
G
I
N
4
D
I
G
I
N
5
C
0
4
4
3
2
8
D
C
T
R
L
-
X
5
/
2
8
X
5
D
I
G
I
N
-
C
I
N
H
1
R
E
F
R
E
F
-
N
-
I
N
R
E
F
-
P
H
I
-
I
N
R
E
F
-
N
-
S
E
T
R
E
F
-
P
S
E
T
R
E
F
-
O
N
R
E
F
-
B
U
S
Y
R
E
F
-
O
K
R
E
F
-
M
A
R
K
C
0
9
2
9
C
0
9
2
3
C
0
9
2
8
C
0
9
2
2
C
0
9
2
7
/
2
C
0
9
2
1
C
0
9
2
7
/
1
C
0
9
2
0
C
T
R
L
C
0
9
3
5
C
0
9
3
6
C
0
9
3
1
C
0
9
3
2
C
0
9
3
0
C
0
9
3
4
C
0
9
3
3
R
E
F
-
P
O
S
-
L
O
A
D
R
E
F
-
A
C
T
P
O
S
-
I
N
C
0
9
2
6
/
1
C
0
9
2
5
C
0
9
2
7
/
3
C
0
9
2
4
C
0
9
2
6
/
3
C
0
9
2
6
/
4
1
0
C
0
1
0
5
C
0
2
5
4
+
-
C
0
9
0
8
C
0
0
7
0
C
0
0
7
1
+
-
1
+
1
0
C
0
0
2
2
C
0
0
8
1
C
0
0
8
7
C
0
0
8
8
C
0
0
8
9
C
0
0
9
0
C
0
0
9
1
P
W
M
C
0
4
2
0
C
0
4
9
0
C
0
4
9
5
M
C
T
R
L
-
P
H
I
-
S
E
T
M
C
T
R
L
-
N
2
-
L
I
M
M
C
T
R
L
-
M
-
A
D
D
M
C
T
R
L
-
P
H
I
-
L
I
M
M
C
T
R
L
-
P
H
I
-
O
N
C
0
9
0
6
/
2
M
C
T
R
L
-
N
-
S
E
T
V
E
C
T
-
C
T
R
L
M
C
T
R
L
-
N
S
E
T
2
M
C
T
R
L
M
C
T
R
L
-
N
A
C
T
M
C
T
R
L
-
P
H
I
-
A
C
T
C
0
9
0
6
/
6
C
0
9
0
6
/
1
M
C
T
R
L
-
N
/
M
-
S
W
T
1
0
M
C
T
R
L
-
H
I
-
M
-
L
I
M
M
C
T
R
L
-
L
O
-
M
-
L
I
M
C
0
0
5
1
+
+
C
0
0
5
0
C
0
0
1
8
C
0
0
0
6
C
0
0
8
4
C
0
0
8
5
C
0
0
8
6
C
0
0
2
5
M
C
T
R
L
-
M
M
A
X
C
0
9
0
9
C
0
0
1
1
1
0
0
%
C
0
0
7
2
C
0
9
0
6
/
5
C
0
9
0
7
/
1
M
C
T
R
L
-
F
L
D
-
W
E
A
K
C
0
9
0
6
/
7
M
C
T
R
L
-
I
-
S
E
T
C
0
9
0
6
/
8
M
C
T
R
L
-
I
-
L
O
A
D
C
0
9
0
7
/
4
M
C
T
R
L
-
Q
S
P
C
0
9
0
7
/
3
C
0
9
0
7
/
2
C
0
9
0
6
/
3
C
0
9
0
6
/
4
C
0
8
9
3
C
0
8
9
2
C
0
8
9
9
C
0
9
0
0
C
0
9
0
2
C
0
9
0
1
C
0
8
9
0
C
0
8
9
4
C
0
8
9
5
C
0
8
9
7
C
0
8
9
6
C
0
8
9
1
C
0
8
9
8
M
C
T
R
L
-
Q
S
P
-
O
U
T
D
C
T
R
L
-
Q
S
P
1
M
C
T
R
L
-
M
A
C
T
M
C
T
R
L
-
D
C
V
O
L
T
C
0
0
4
2
M
C
T
R
L
-
P
H
I
-
A
N
A
C
O
N
S
T
+
+
C
0
4
9
7
R
E
S
O
L
V
E
R
X
7
E
N
C
O
D
E
R
X
8
M
C
T
R
L
-
P
H
I
-
A
N
G
C
0
0
7
5
C
0
0
7
6
C
0
0
7
7
C
0
0
7
8
Q
S
P
decel. ramp
A
1
A
2
A
3
A
4
1
0
C
0
1
1
8
/
1
.
.
.
4
D
I
G
O
U
T
1
D
I
G
O
U
T
2
D
I
G
O
U
T
3
D
I
G
O
U
T
4
C
0
1
1
7
/
1
C
0
1
1
7
/
2
C
0
1
1
7
/
3
C
0
1
1
7
/
4
C
0
4
4
4
/
4
C
0
4
4
4
/
3
C
0
4
4
4
/
2
C
0
4
4
4
/
1
X
5
1
AOUT2
DIGOUT
AOUT1
M
M
C
C
T
T
R
R
L
L
-
-
M
M
S
S
E
E
T
T
2
1
M
C
T
R
L
-
I
M
A
X
C
0
0
5
6
M
C
T
R
L
-
I
A
C
T
9300STD325
Fig. 12-6 Signal flow diagram for configuration 6000