363-206-285
Circuit Pack Descriptions
Issue 3 June 2001
7-29
Timing Circuitry 7
The timing distribution to the DS1 contains ten timing signals: two high-speed
clocks (active and standby), four VT-G clocks (two active and two standby), and
four frame sync signals (two active and two standby).
The DS1 receives from the MXRVO/STS1E a synchronous transport signal
(STS-1) rate high-speed clock that provides the frequency reference for the
desynchronizing phase-locked loop. This high-speed reference clock is also used
to synthesize the DS1 rate AIS clock source for the DS1 devices and to provide a
DS1 test signal.
The DS1 uses the VT-G clocks (6.912 MHz) and the frame sync signals it receives
from the MXRVO/STS1E to clock VT-G data to/from the MXRVO/STS1E.
Protection Circuitry 7
Optional 1x7 revertive DS1 circuit pack protection is provided and this protection
is independent of the MXRVO/STS1E circuit pack(s). The DS1 protection switch
points are implemented with on-board relays on the DSX-1 side and with logic
selectors at the VT-G level on the active and standby MXRVO/STS1E circuit
packs. The SYSCTL controls these relays through two serial interfaces so that a
failure of one serial interface to the DS1 does not prevent control of the relays. If
+5 V power on the DS1 fails, the relays default to the protection state. If the
SYSCTL is removed, the relays remain in their current state.
Shorting contacts are provided in the DS1 backplane connector so that when the
circuit pack is removed, the DSX-1 cable pairs short through to the protection bus.
!
CAUTION:
Unused low-speed interface slots within a partially equipped group must be
equipped 177A Retainer cards if DS1 protection is used. Failure to do so
may result in corrupted transmission. The BBF3 DS1PM circuit pack can be
mixed with the BBF1/1B. If mixed, the protection circuit pack must be a
BBF3 DS1PM.
When a DS1 circuit pack is inserted, the relays are in the protection state until the
SYSCTL determines that the circuit pack is good.
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