363-206-285
Shelf Descriptions and Configurations
3-24 Issue 3 June 2001
Transmultiplexer 3
The DS3 Transmux interface circuit pack (TMUX) provides a mapping between
the DS3 low-speed signal and internal STS-1 signals. Up to three DS3 interfaces
(1x1 protected) may be supported per shelf. Figure 3-15 shows TMUX packs in
function unit A.
In the transmit direction, the BBG20 TMUX circuit pack accepts one 44.736 Mb/s
bipolar 3-zero substitution (B3ZS) coded DS3 signal and demultiplexes it into 28
DS1s. Performance monitoring is performed on the DS1s before they are mapped
into floating VT1.5s. The 28 VT1.5s are then multiplexed into STS-1 payload
envelope(s) using SONET asynchronous mapping. The STS-1 path overhead and
pointer bytes are added and the resulting signal is sent to the high-speed OLIU
circuit pack.
In the receive direction the reverse process takes place: The STS-1 signal(s) from
the OLIU circuit pack goes through STS-1 pointer interpretation, path overhead is
removed and processed, and the twenty-eight VT1.5s are stripped of their
overhead to produce 28 DS1s. The DS1s are then multiplexed back into the DS3.
Equipping the main slots with 24-type or 29-type OLIUs allows the shelf to provide
an OC-12 ring interface.
Figure 3-15. OC-3/OC-12 Shelf with Transmultiplexers
1
C
T
G
2
T
G
1
O
L
I
U
O
L
I
U
111
A
B
S
Y
S
C
T
L
U
S
E
R
A
N
E
L
P
AUXCTL
SYSCTL
2(P) 2(P) 2(P) 2(P)
O
H
C
T
L
Timing Main
Group A Group B Group C
Function Units
Low Speed
T
M
U
X
T
M
U
X
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