363-206-285
Circuit Pack Descriptions
7-48 Issue 3 June 2001
SYSCTL controls these relays through two serial interfaces so that a failure of one
serial interface to the HDSL does not prevent control of the relays. If +5V power
on the HDSL fails, the relays default to the protection state.
Shorting contacts are provided in the HDSL backplane connector so that when the
circuit pack is removed, the HDSL cable pairs short through to the protection bus.
!
CAUTION:
Unused low-speed interface slots within a partially equipped group must be
equipped with 177A Retainer cards if HDSL protection is used. Failure to do
so may result in corrupted transmission. The HDSL circuit pack can not be
mixed with the BBF1/1B/3Bs.
When a HDSL circuit pack is inserted, the relays are in the protection state until
the SYSCTL determines that the circuit pack is good.
Fault Detection Circuitry 7
The HDSL circuit pack has in-service and out-of-service built-in test capability. In-
service testing is continuous and errors are reported when they occur to the
SYSCTL via the intra-shelf control bus. An out-of-service test is performed
whenever the HDSL circuit pack is inserted or recovers from a transient failure.
The incoming HDSL signal is monitored for HDSL synchronization errors.
Incoming VT1.5 signals are monitored for VT AIS, VT LOP, and yellow.
Loopbacks 7
The HDSL circuit pack has two types of loopback, terminal and facility. Both types
are controlled by the SYSCTL via the intra-shelf control bus. The two loopbacks
must be done independently.
The terminal loopback is provided on the HDSL circuit pack for each HDSL
interface. The loopback is done inside the VT1.5 processor device and bridges
the desynchronizer output signal (transmitted towards the far-end HDSL
equipment) back to the DS1 synchronizer input. When the loopback is operated,
the DS1 interface device forces AIS towards the far-end HDSL equipment.
The facility loopback is provided for both HDSL signals on the circuit pack. When
this loopback is completed, all DS1 clock and data signals received from the
VT1.5 processor are simultaneously looped back toward the far-end HDSL
equipment. The loopback is a bridge, so the transmitted DS1 signals (towards the
high-speed interface) are not affected.
Optional HDSL Settings 7
All system settings are stored in NVRAM at the unit designated as the system
Master. Access to these settings is through the RS-232 faceplate port only. These
settings are downloaded to the slave unit at system synchronization and at regular
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