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Circuit Pack Descriptions
7-54 Issue 3 June 2001
LAN Interface (BBF9) 7
■ Electrical Specification:
The BBF9 LAN circuit pack provides a single 10/100BaseT, IEEE 802.3
compliant interface. The LAN port performs protocol transparent filtering
and bridging of incoming MAC frames. MAC frames with a destination
address on the local bus are filtered by the BBF9 to prevent unnecessary
transmission of frames over the wide area network (WAN). The LAN
interface autonegotiates mode (full/half duplex) and speed (10/100 Mb/s)
when interfacing with other 802.3 compliant devices over twisted pair
media. The circuit pack occupies two adjacent low-speed slots and uses
from one to 8 DS1 signals to provide native mode LAN transport through a
SONET WAN.
■ LAN port:
— 10/100BaseT IEEE 802.3 compliant
— RJ-45 faceplate connector
— Cat-3 or CAT-5 UTP (unshielded twisted pair) medium
— Buffering .5 MByte for each direction
■ Format Specification:
The LAN interface converts incoming MAC frames to an ATM cell format
using ATM adaptation layer 5 (AAL5) encapsulation as specified in IETF
RFC-1483. ATM cells are distributed in round robin order on 1 to 8 ESF
formatted DS1 signals using the ATM forum IMA Specification Version 1.1
for inverse multiplexing. The DS1 signals are mapped into asynchronous
VT1.5 signals, four of which are muxed to create a VT-G for transport
through a SONET network. Two VT-G signals are sent to the MXRVO for
multiplexing into an STS-1. The circuit pack can compensate for up to 50
ms of differential delay among the 8 DS1s and uses a single IMA group
with one ATM virtual channel (VC). The following provisioning options are
provided:
— AAL5 Protocol - VC multiplex or LLC encapsulation (Bridged)
— MAC Frame Check Sequence (FCS) Preservation - enable or
disable
— ATM Virtual Path ID and Virtual Channel ID
— IMA group ID
— IMA Frame Length - 32, 64, 128, 256
— ATM scrambler - on/off
— ATM polynomial - on/off.
The IMA link IDs are assigned automatically by the system in the range 0 to
7. The IMA protocol operates in symmetric configuration with common
clock.
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