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Circuit Pack Descriptions
7-58 Issue 3 June 2001
Timing Circuitry 7
The timing distribution to the IMA LAN contains timing signals: four high-speed
clocks (active and standby), eight VT-G clocks (four active and four standby), and
eight frame sync signals (two active and two standby).
Fault Detection Circuitry 7
The DS1 circuit pack has in-service and out-of-service built-in test capability. In-
service testing is continuous and errors are reported when they occur to the
SYSCTL via the intra-shelf control bus. An out-of-service test is performed
whenever the DS1 circuit pack is inserted or recovers from a transient failure. The
incoming DS1 signals are monitored for DS1 OOF. Incoming VT1.5 signals are
monitored for VT AIS, VT LOP, and yellow.
Loopbacks 7
The IMA LAN circuit pack has a DS1 terminal loopback controlled by the SYSCTL
via the intra-shelf control bus.
The terminal loopback is provided on the circuit pack for each DS1. The loopback
is done inside the MUX/DEMUX/DESYNC device and bridges the desynchronizer
output signal (transmitted towards the DSX-1) back to the DS1 synchronizer input.
Performance Monitoring 7
In addition to DS1 path and VT1.5 path performance monitoring, the BBF9/BBF10
circuit pack supports performance monitoring of data flow in both directions. The
parameters supported are:
— Transmit MAC packets forwarded (towards the WAN)
— Transmit MAC packets discarded
— Receive MAC packets forwarded (towards the LAN)
— Receive MAC packets discarded.
In addition, to monitor the efficiency of the IMA link the following parameters are
supported:
— Transmit ATM cells total
— Transmit ATM idle cells
— Receive ATM cells total
— Received ATM cells Idle.
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