Diagram
Bits
7 6 5 4 3 2 1 0
R
GCA
W
RRST
SW4[7:8] 111111
Fields
Field Function
7-6
GCA
General Purpose Configuration Inputs (cfg_gpin):
XX= Value for cfg_gpin[7:6].
5-0
-
Reserved.
3.56 IRQ Management Registers
The IRQ control and status registers may be used to monitor and control the behavior of various interrupt (IRQ, EVT, and
TMPDET) signals.
IRQSTATn registers show the real-time status of connected interrupt pins. Interrupts have device-defined polarities, so no
interpretation is made as to whether a signal is considered asserted or deasserted.
IRQCTLn registers allow control of interrupt drive options of level-sensitive or edge-sensitive, with active-high or -low assertion.
Not all interrupts have this facility.
IRQDRVn registers allows forcing interrupt pins to a high or low state. The IRQDRV settings take priority over interrupt sources,
so these registers may optionally be used to implement interrupt masks.
Interrupt Assignments
Interrupt Assignment Has CTL
IRQ1 IN112525 PHY LOL Y
IRQ6 (none) N
IRQ7 Fan interrupt (from EMC2305) N
IRQ9 IN112525 PHY LOL if SFP2 MOD_ABS low Y
IRQ10 IN112525 PHY LOL if SFP3 MOD_ABS low Y
IRQ11 zQSFP+ transceiver (40G PHY) interrupt N
TMPDETB TMP_DETECT_B N
NXP Semiconductors
Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 102 / 116
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