With power available, CPLD can manage the orderly power-up of the rest of the system on an appropriate event (one of the
following):
• The power switch (push button) is pressed
• The SW_AUTO_ON switch (SW4[2]) is set to '1'
On receipt of a power event signal, the CPLD power sequencer block manages the orderly enable of the remaining power supplies,
as shown in the figure below.
Vac (ATX-PS)
5V0_SB
HOT_POWER
1V5_SB,
3V3_SB
TA_BB_VDD
PS_ON_B
TIER 0
3V3, 5V0, 12V0
USB_HVDD
ATXPWRGD
TIER 1
0V85, 0V9, 1V2
TIER 2
VDD, OVDD,
2V1, 2V5,
USB_SVDD
PORESET_B
~12mS
~11mS
220-250mS
~500mS
530mS
550-570mS
570-590mS
~610mS
>= 700mS
t
TIER 3
SD_SVDD,
SD_OVDD,
AVDD_SDn_PLLn
TIER 4
GVDD,
VTT1, VTT2,
DDR_VREF,
EVDD
Figure 7. Power up voltage sequence
The LX2160ARDB follows the power supply sequencing requirements as detailed in
QorIQ LX2160A Data Sheet
.
2.1.4 Current and power measurements
The LX2160ARDB implements onboard current and power measurements only for the VDD supply. For selected other supplies,
monitoring resistors are available. The table below lists all measurable supplies.
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 17 / 116
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