Table 26. Reset Sequencer state (continued)
State LED: M[3:0] Description
CLOCK_LOCK 0101 = 0x5 Wait for clock PLLs to stabilize
RELEASE_ALL 0110 = 0x6 Release all hardware resets except DUT
RELEASE_DUT 0111 = 0x7 Release DUT from reset
STABLE 1000 = 0x8 Reset sequencing complete. Wait for reset events.
RESET_REQ 1001 = 0x9 Start reset due to DUT RESET_REQ_B
PORESET 1010 = 0xA Start reset due to JTAG_RST_B
RST_WATCH 1011 = 0xB Start reset due to watchdog timeout
RST_BY_REG 1100 = 0xC Start reset due to setting register bit RST_CTL[RST] = 1
RST_BY_SW 1101 = 0xD Start reset due to pushbutton switch
RECONFIG 1110 = 0xE Start reset due to reconfig request via RCFG[GO] = 1
POST_RST 1111 = 0xF Wait for reset requests to clear
2.19 System controller
The LX2160ARDB system controller (or “CPLD” for short) controls the operation of the system, including:
• AC power supply control
• Onboard regulator control and sequencing
• Reset assertion to processor and devices
• Processor and system configuration
• Interrupt management
• System alert monitoring and status display
• Remapping of system boot devices
• Handling of board control and status registers
The following two figures show the system controller architectural details.
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 49 / 116
To Next Page
Loading...
