• Memory interface includes all necessary termination and I/O power
• Memory signals are routed in a way to achieve maximum performance on the bus
By default, one of the two DIMM sockects of each LX2160ARDB DDR port has a DIMM installed. It is a 288-pin, dual-rank, 16
GB DDR4 SDRAM UDIMM (MTA18ADF2G72AZ-3G2E1), which supports 64-bit data with 8-bit ECC and operates at up to 3.2
GT/s (0.62 ns frequency at column access strobe (CAS) latency = 22).
The LX2160ARDB DDR interface can work with any JEDEC-compliant, 288-pin, DDR4 UDIMM or RDIMM module.
The DIMM used in the board is a representative DIMM.
NOTE
2.3.1 DDR power
The LX2160ARDB power supplies provide the voltages shown in the table below specifically for the DDR4 subsystem (see Power
supplies for further details).
Table 9. DDR power supplies
Voltage name Voltage Current Description
GVDD 1.2 V <= 20 A DDR and processor I/O power
VTT1 0.6 V <= 3 A DDR#1 termination supply
VTT2 0.6 V <= 3 A DDR#2 termination supply
2.4 SerDes interface
The LX2160A processor supports three SerDes modules (SerDes1, SerDes2, and SerDes3), each having eight high-speed serial
communication lanes. Each SerDes lane supports speeds of up to 25 GHz.
The figure below shows the LX2160ARDB SerDes architecture.
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 23 / 116
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