LX2160A
GPIO
event
header
90120-0125
4.7 K (weak)
(17 places)
OVDD
4
3
2
1
5
OVDD (1.8 V)
PHY_25G_LOL/IRQ1
IRQ6
IRQ_FAN_B/IRQ7
PHY_25G_LOL/IRQ9
PHY_25G_LOL/IRQ10
IRQ_QSFP_B/IRQ11
IRQ_40GE_B/IRQ0
IRQ_10G_PHY1_B/IRQ2
IRQ_10G_PHY2_B/IRQ3
IRQ_EPHY1_B/IRQ4
IRQ_EPHY2_B/IRQ5
IRQ_RTC_B/IRQ8
EVT0
EVT1
EVT2
EVT3
EVT4
CS4223 40 GbE PHY
AQR107 10 GbE PHY #1
AQR107 10 GbE PHY #2
AR8035 1 GbE PHY #1
AR8035 1 GbE PHY #2
RTC
IN112525 25 GbE PHY
IN112525 25 GbE PHY
IN112525 25 GbE PHY
zQSFP+ 40 GbE module
EMC2305 fan controller
Figure 26. Interrupt architecture
The table below summarizes the interrupt assignments used.
Table 18. LX2160ARDB interrupt assignments
Interrupt signal Supported function Description
IRQ0_B IRQ_40GE_B 40 GbE PHY (CS4223) interrupt
IRQ1_B PHY_25G_LOL 25 GbE PHY (IN112525) loss-of-lock interrupt
IRQ2_B IRQ_10G_PHY1_B 10 GbE PHY #1 (AQR107) interrupt
IRQ3_B IRQ_10G_PHY2_B 10 GbE PHY #2 (AQR107) interrupt
IRQ4_B IRQ_EPHY1_B 1 GbE PHY #1 (AR8035) interrupt
IRQ5_B IRQ_EPHY2_B 1 GbE PHY #2 (AR8035) interrupt
IRQ6_B Unassigned
IRQ7_B IRQ_FAN_B EMC2305 fan controller interrupt
IRQ8_B IRQ_RTC_B RTC interrupt
IRQ9_B PHY_25G_LOL (if SFP2_MOD_ABS is low) SFP2 transceiver loss-of-lock interrupt
IRQ10_B PHY_25G_LOL (if SFP3_MOD_ABS is low) SFP3 transceiver loss-of-lock interrupt
IRQ11_B IRQ_QSFP_B zQSFP+ transceiver (40 GbE PHY) interrupt
2.15 GPIO access
The LX2160A processor has no dedicated general-purpose input/output (GPIO) pins. Instead, GPIO functions are multiplexed
internally onto other signals, which must be disabled before using the GPIO functions. For the LX2160ARDB, GPIO access is
provided through the IRQ pins IRQ[0:11] and EVT pins EVT[0:4] but only when those pins are not used for IRQ or other purposes.
The following figure shows the GPIO access header.
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 39 / 116
To Next Page
Loading...
