Diagram
Bits
7 6 5 4 3 2 1 0
R DDRCLK SYSCLK
W
NONE 0000 0000
Fields
Field Function
7-4
DDRCLK
DDRCLK Rate Selection:
0000= 100.00 MHz (fixed)
Other values are Reserved.
3-0
SYSCLK
SYSCLK Rate Selection:
0000= 100.00 MHz (fixed)
Other values are Reserved.
3.32 Clock ID/Status (CLK_ID)
Address
Register Offset
CLK_ID 033h
Function
The CLK_ID register is used to identify the arrangement of the clock control registers. Software should check CLK_ID register
before attempting to interpret/control the clock control registers.
Diagram
Bits
7 6 5 4 3 2 1 0
R ID
W
NONE 0000 0000
Fields
Field Function
7-4 Reserved.
Table continues on the next page...
NXP Semiconductors
Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 82 / 116
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