Diagram
Bits
7 6 5 4 3 2 1 0
R
W
RRST
11111111
Fields
Field Function
7-0
-
Reserved.
3.52 DUT Configuration 2 (DUTCFG2)
Address
Register Offset
DUTCFG2 062h
Function
The DUTCFG2 register manages processor device selection (SVR) and internal-only device test features.
Diagram
Bits
7 6 5 4 3 2 1 0
R
SVR10 TEST
W
RRST
11111 SW3[2:3] SW3[1]
Fields
Field Function
7-3
-
Reserved.
2-1
SVR10
Controls System Version (config cfg_svr[1:0]):
XX= Selected processor variant (refer to the device Reference Manual).
NOTE: SVR settings must match installed device.
0 Controls Test Select (config TEST_SEL_B):
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NXP Semiconductors
Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 99 / 116