Table 10. LX2160ARDB SerDes assignments
SerDes
module
Lane Connectivity Port
SerDes1 H / 0 Aquantia AQR107 10 GbE PHY #1 2x 10 GbE RJ45 USXGMII magnetic jacks (10G
MAC3/4)
G / 1 Aquantia AQR107 10 GbE PHY #2
F-E / 2-3 Inphi IN112525 25 GbE PHY 2x 25 GbE SFP+ fiber transceiver cages (25G
MAC5/6)
D-A / 4-7 Inphi CS4223 40 GbE PHY 40 GbE QSFP+ fiber transceiver cage (40G
MAC2)
SerDes2 A-D / 0-3 PCI Express (Gen 1/2/3) PCI Express x4 connector (slot 1)
1
E / 4 SATA SATA header 3
F / 5 SATA SATA header 4
G / 6 SATA SATA header 1
H / 7 SATA SATA header 2
SerDes3 A-H / 0-7 PCI Express (Gen 1/2/3) PCI Express x8 connector (slot 2)
1. A right-angle adapter is required to connect a PCIe Gen 1/2/3 connector.
No muxes or other configuration is required for SerDes operation.
NOTE
2.5 Ethernet controller interface
The LX2160A processor supports two Ethernet controllers, EC1 and EC2, supporting the RGMII protocol. On the LX2160ARDB,
each Ethernet controller is connected to a 1 GbE RGMII Ethernet PHY (Qualcomm AR8035), which is connected to an RJ45 jack
coupled with magnetics. The two RJ45 jacks are stacked on the board such that jack for EC1 is at the bottom and jack for EC2
is at the top.
The figure below shows the architecture of the Ethernet controller interface.
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 25 / 116
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