Table 17. I2C bus device map (continued)
I2C bus 7-bit address Device Description Notes
I2C1_CH7_CH0 0x50 Quad SFP+ cage 40G MAC2 QSFP+ port
I2C1_CH7_CH1 Unused
I2C1_CH7_CH2 Unused
I2C1_CH7_CH3 Unused
I2C1_CH7_CH4 0x50 SFP+ cage (#1) 25G MAC5 SFP port
I2C1_CH7_CH5 0x50 SFP+ cage (#2) 25G MAC6 SFP port
I2C1_CH7_CH6 - PCIe slot 1 PCIe slot 1
I2C1_CH7_CH7 - PCIe slot 2 PCIe slot 2
I2C2 Unused
I2C3 Unused
I2C4 Unused
I2C5 0x51 NXP PCF2129AT Real-time clock Provides real-time clock
0x54 - 0x57 Microchip AT24CM02-
SSHM-B: 256 KB
EEPROM
UEFI storage Provides UEFI variable
storage in four logical
devices
I2C6 - Aquantia AQR107 PHY
(#1)
10 Gbit Ethernet PHY 1 Optional, software-
defined address
- Aquantia AQR107 PHY
(#2)
10 Gbit Ethernet PHY 2 Optional, software-
defined address
A 7-bit address does not include the read/write (R/W) bit as an address member, though some datasheets might
do so. For consistency, all I2C addresses above are of 7 bits only.
NOTE
To access I2C devices on the secondary I2C mux, the primary I2C mux needs to be programmed at address 0x77
and the secondary I2C mux at address 0x75.
NOTE
2.11 UART interface
The LX2160A processor provides two UART blocks, which support two full serial ports with hardware flow control, or four serial
ports with no flow control. On the LX2160ARDB, the UART ports are available for external connection through a dual-port stacked
DB9 male connector. Two RS-232 transceivers (Linear Technology LTC2804-1) translate the signals to RS-232 levels. The figure
below shows the UART architecture.
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 36 / 116
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