Table 28. Non-processor configuration settings
Configuration signal DIP switch CPLD register Description
CFG_XSPI_MAP[0:3] SW1[6:8] BRDCFG0[7:5] Controls how XSPI_A chip-selects are connected
to devices/peripherals
CFG_MUX_EC2 - BRDCFG4[7] Controls the configuration of Ethernet controller 2
CFG_IEEE_SRC - BRDCFG4[6] Selects the source for IEEE clock
CFG_CAN_EN_B - BRDCFG4[5] Enables/disables CAN transceivers
CFG_40GE_ROM SW2[2] BRDCFG4[4] Controls the configuration of the CS4223 40 GbE
PHY
CFG_SPREAD SW2[1] BRDCFG4[0] Controls whether clocks for PCIe slots are
spread-spectrum modulated or fixed
CFG_MEM_WP SW4[3] Allows/prevents write to SYSID and I2C flash
2.19.2 System startup
The system controller manages the orderly startup of the system by managing power enables and reset assertion (including
device configuration), in the order shown in the table below.
Table 29. Startup sequence
Controller Step Action Description
Power sequencer
1 Wait for power-on event. Triggered by the SW_PWR_B signal, or by setting switch
SW_AUTO_ON=1.
2 Enable ATX power supply. Enable ATX PSU, wait for it to report “power good”.
LX2160A PORESET_B is asserted during power-up.
3 Apply power to group 1 power
supplies.
Enable group 1 power supplies, wait for all members to
report “power good” (if supported):
• 0V85
• 0V9
• 1V2
• 2V1
• 2V5
• OVDD
• EVDD
• USB_SVDD
4
Apply power to group 2 power
supplies.
Enable group 2 power supplies, wait for all members to
report “power good” (if supported):
• VDD
• SD_SVDD
Table continues on the next page...
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 53 / 116
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