NXP Semiconductors QorIQ LX2160A - 3.30 Clock Control Registers

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Field Function
5-4
SD1CK2
SerDes1 Clock #2 (S) Rate:
11= 161.1328125 MHz (fixed)
3-2
SD2CK1
SerDes2 Clock #1 (F) Rate:
00= 100.0000000 MHz (fixed)
1-0
SD2CK2
SerDes2 Clock #2 (S) Rate:
00= 100.0000000 MHz (fixed)
3.47 Board Configuration 3 (BRDCFG3)
Address
Register Offset
BRDCFG3 053h
Function
The BRDCFG3 register reports SerDes clock speeds for SerDes block 3. PCIe clocks may be fixed or spread-spectrum enabled,
as selected by BRDCFG4.SPREAD.
Diagram
Bits
7 6 5 4 3 2 1 0
R SD3CK1 SD3CK2
W
RRST 00 00 0000
Fields
Field Function
7-6
SD3CK1
SerDes3 Clock #1 (F) Rate:
00= 100.0000000 MHz (fixed)
5-4
SD3CK2
SerDes3 Clock #2 (S) Rate:
00= 100.0000000 MHz (fixed)
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NXP Semiconductors
Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 95 / 116