NXP Semiconductors QorIQ LX2160A - 1.2 Related documentation

Table 3. LX2160ARDB features (continued)
LX2160ARDB feature Specification Description
• 1.2 V (G1VDD and G2VDD) for DDR4
• 0.92 V (SD_SVDD) for SerDes cores
• 1.8 V (SD_OVDD) for SerDes I/O drivers
• 0.9 V (SD_AVDD) for SerDes PLLs
• 1.8 V (OVDD) for general I/O
• 1.8 V (standby) and 3.3 V (standby) for CPLD core and I/O
• 0.8 V for USB_SVDD and USB_SDVDD
• 3.3 V for USB_HVDD
• 0.8 V (TA_BB_VDD) for the LX2160A secure monitor
• 1.8 V for TA_PROG_SFP and PROG_MTR
Debug features Arm Cortex 10-pin JTAG connector
System logic CPLD
• Manages the following:
— System power sequencing
— System reset sequencing
— System and SerDes clock speed selections
— SoC POR configuration at reset
• Implements registers for system control and monitoring
• General fault monitoring and logging
1.5 Board top view
The figure below shows the top-side view of the LX2160ARDB.
Figure 2. LX2160ARDB top view
NXP Semiconductors
LX2160ARDB Overview
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 9 / 116