Table 30. Qixis Register Memory Map (continued)
Offset Register
Width
(In bits)
Access Reset value
06Bh
DUT Configuration 11 (DUTCFG11) 8 RW xxx11111b
06Ch
DUT Configuration 12 (DUTCFG12) 8 RW xx111111b
090h
Interrupt Status 0 (IRQSTAT0) 8 RO 11111111b
091h
Interrupt Status 1 (IRQSTAT1) 8 RO 11111111b
094h
Interrupt Control 0 (IRQCTL0) 8 RW 00000000b
096h
Interrupt Control 2 (IRQCTL2) 8 RW 00000000b
098h
Interrupt Drive 0 (IRQDRV0) 8 RW 00000000b
099h
Interrupt Drive 1 (IRQDRV1) 8 RW 00000000b
09Ah
Interrupt Drive 2 (IRQDRV2) 8 RW 00000000b
09Dh
Interrupt Drive 5 (IRQDRV5) 8 RW 00000000b
0D8h
Core Management Address (CMSA) 8 RW 00000000b
0D9h
Core Management Data (CMSD) 8 RW 00000000b
0DCh
Switch Control (SWS_CTL) 8 RW 00000101b
0DDh
Switch Sample Status (SWS_STAT) 8 RO 10000000b
3.1 Register Conventions
An undefined register address does not have any defined register value. Reads and writes to such addresses should be avoided.
If you attempt to read such addresses, undefined data is returned. Undefined register addresses may be defined in the future.
For registers which do not define all bits, reserved bits behave as follows:
Reserved Bits
Register Recommended Actions
DUTCFG Read as 1. Write ones to unused bits.
others Read as 0. Write zeroes to unused bits.
Future definitions of reserved bits will maintain backward compatibility with the above rules.
3.2 Resets
The reset values for registers are defined as follows:
NXP Semiconductors
Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 58 / 116
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