NXP Semiconductors QorIQ LX2160A - Page 57

Table 30. Qixis Register Memory Map (continued)
Offset Register
Width
(In bits)
Access Reset value
021h
Power Control 2 (PWR_CTL2) 8 RW 00000000b
022h
Power Event Trace (PWR_EVENT) 8 RO 00000000b
024h
Power Status 0 (PWR_MSTAT) 8 RO 11001011b
025h
Power Status 1 (PWR_STAT1) 8 RO 11111111b
026h
Power Status 2 (PWR_STAT2) 8 RO 11111111b
030h
Clock Speed 1 (CLK_SPD1) 8 RO 00000000b
033h
Clock ID/Status (CLK_ID) 8 RO 00000000b
040h
Reset Control (RST_CTL) 8 RW 00xx0000b
041h
Reset Status (RST_STAT) 8 RO 00000000b
042h
Reset Event Trace (RST_REASON) 8 RO 11110000b
043h
Reset Force 1 (RST_FORCE1) 8 RW 00000000b
044h
Reset Force 2 (RST_FORCE2) 8 RW 00000000b
045h
Reset Force 3 (RST_FORCE3) 8 RW 00000000b
04Bh
Reset Mask 1 (RST_MASK1) 8 RW 00000000b
04Ch
Reset Mask 2 (RST_MASK2) 8 RW 00000000b
04Dh
Reset Mask 2 (RST_MASK3) 8 RW 00000000b
050h
Board Configuration 0 (BRDCFG0) 8 RW xxx00000b
051h
Board Configuration 1 (BRDCFG1) 8 RO 00000000b
052h
Board Configuration 2 (BRDCFG2) 8 RO 11110000b
053h
Board Configuration 3 (BRDCFG3) 8 RO 00000000b
054h
Board Configuration 4 (BRDCFG4) 8 RW 000x0x0xb
060h
DUT Configuration 0 (DUTCFG0) 8 RW 0000xxxxb
061h
DUT Configuration 1 (DUTCFG1) 8 RW 11111111b
062h
DUT Configuration 2 (DUTCFG2) 8 RW 11111xxxb
066h
DUT Configuration 6 (DUTCFG6) 8 RW 1111111xb
Table continues on the next page...
NXP Semiconductors
Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
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