LX2160A
I1588_PULSE_OUT[2:1]
I1588_ALARM_OUT[1:2]
I1588_TRIG_IN[1:2]
TSM-106-01-S-DV-A-P
ALARMO[1:2]
TRIGIN[1:2]
CLK_OUT
CLK_IN
PULSEO[2:1]
Clock mux
CPLD
I1588_CLK_OUT
1588 access header
I1588_CLK_IN
RST_IEEESLT_B
1
2
3
4
5
6
7
8
9
10
11
12
OVDD (1.8 V)
(1,3)
(2,4)
(5,7)
(8)
(6)
RCLK0
IEEE_RCLK0
(9)
(10)
IEEETEST_CLKIN
3V3
CFG_IEEE_SRC
Si5341B
CLK_1588_CGEN
Figure 14. IEEE 1588 architecture
The table below lists the testing options provided by the IEEE 1588 test header.
Table 11. IEEE 1588 port
IEEE 1588 feature Specifications Description
Clocks Input clock Ethernet reference clock (to processor) is driven from an onboard 125 MHz
oscillator source. Under software configuration, it may be clocked from the
IEEE 1588 header instead.
Output clock Ethernet output clock is driven to the IEEE 1588 header
Signals Other related signals All remaining IEEE 1588 signals are connected to the dedicated header pins
2.6 Ethernet management interface
The LX2160ARDB has two Ethernet management interfaces, EMI1 and EMI2, for controlling PHY transceivers. The figure below
shows the PHY device connections.
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 27 / 116
To Next Page
Loading...
