NXP Semiconductors QorIQ LX2160A - 3.29 Power Status 2 (PWR_STAT2)

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Field Function
5-4
DDRCLK
DDRCLK Frequency Selection:
00= 100.00 MHz (fixed)
All other values are reserved.
3-2
-
Reserved.
1-0
SYSCLK
SYSCLK Frequency Selection:
00= 100.00 MHz (fixed)
All other values are reserved.
3.46 Board Configuration 2 (BRDCFG2)
Address
Register Offset
BRDCFG2 052h
Function
The BRDCFG2 register reporst SerDes clock speeds for SerDes blocks 1 and 2. PCIe clocks may be fixed or spread-spectrum
enabled, as selected by BRDCFG4.SPREAD.
Diagram
Bits
7 6 5 4 3 2 1 0
R SD1CK1 SD1CK2 SD2CK1 SD2CK2
W
RRST 11 11 00 00
Fields
Field Function
7-6
SD1CK1
SerDes1 Clock #1 (F) Rate:
11= 161.1328125 MHz (fixed)
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NXP Semiconductors
Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 94 / 116