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Field Function
3-0
-
Reserved.
3.48 Board Configuration 4 (BRDCFG4)
Address
Register Offset
BRDCFG4 054h
Function
The BRDCFG4 register controls general board configuration.
Diagram
Bits
7 6 5 4 3 2 1 0
R
EC2 IEEECLK CAN_EN ROM40G I2C40G SLOTCLK SPRLVL SPREAD
W
RRST
0 0 0 SW2[2] 0 SW2[3] 0 SW2[1]
Fields
Field Function
7
EC2
Ethernet2 Configuration (net CFG_MUX_EC2):
0= Processor EC2 pins connect to Ethernet PHY #2.
1= Processor EC2 pins connect IEEE slot (alternate function).
6
IEEECLK
IEEE Clock Source Configuration (net CFG_IEEE_SRC):
0= IEEE clock provided by on-board 125.00 MHz reference.
1= IEEE clock provided by IEEE slot pin 10.
5
CAN_EN
CAN I/O Enable (net CFG_CAN_EN_B):
0= CAN transceivers are disabled.
1= CAN transceivers are enabled.
4
ROM40G
40GE PHY ROM Configuration Enable:
0= CS4223 40GE PHY should power up unconfigured.
1= CS4223 40GE PHY should use its configuration EEPROM for initial settings and DSP software load.
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NXP Semiconductors
Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 96 / 116
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