CPLD
SW1
OVDD=1V8
3V3
IRQ1_B
IRQ[6:7]_B
IRQ[9:11]_B
LX2160A
CPLD
CFG_40GE_ROM
CFG_MUX_EC2
CFG_SPREAD
CFG_CLKEN_SLOT[1:2]_B
CFG_IEEE_SRC
MAX CPLDs do not
have a pulldown
option, so switches
are implemented as
shown. The CPLD
inverts the signals,
so that UP = ON.
CPLDCPLD
1
85432 6 7
ON
1
85432 6 7
ON
SW2
1
85432 6 7
ON
1
85432 6 7
ON
CLK_OUT
XSPI_A_CS[0:1]_B
XSPI_A_SCK
SDHC2_DAT[7:6]
cfg_rcw_src[1:0]
cfg_eng_use[1:2]
cfg_soc_use
cfg_rcw_src3
cfg_eng_use0
cfg_svr[0:1]
cfg_gpin[7:6]
UART[1:2]_SOUT
UART[1:2]_RTS_B
USB1_PWRFAULT
CFG_DRV
SW3
1
85432 6 7
ON
1
85432 6 7
ON
SW4
1
85432 6 7
ON
1
85432 6 7
ON
LED_STAT[7:0]
ASLEEP
RESET_REQ_B
TEST_SEL_B
TBSCAN_EN_B
cfg_rcw_src[2]
cfg_pllcfg_b
TEST_SEL_B
TBSCAN_EN_B
To clocks
CFG_XSPI_MAP[3:0]
To XSPI
To PHYs
CFG_MEM_WP
CFG_CAN_EN_B
To misc
DDR_EVENT_B
VDD_ALERT_B
PRSNT_PROC_B
PRSNT_SLOT[1:2]_B
ROTATION_ERR_B
THERM_WRN_B
THERM_FLT_B
CPU_ID[1:0]
LED_FAIL
LED_PASS
LED_PORST
LED_RSTREQ
LED_ASLEEP
LED_THERM
SW1[1:8]
SW2[1:8]
SW3[1:8]
SW4[1:8]
I2C1_SDA
I2C1_SCL
CTS
218-8LPST
CTS
218-8LPST
CTS
218-8LPST
CTS
218-8LPST
CFG_XTEST
LEDs of
indicated
colors
(RED = alert)
Test-point
Refer to
GSG for
assignments
SFP[2:3]_TX_FAULT
SFP[2:3]_RX_LOS
SFP[2:3]_MOD_ABS
SFP[2:3]_TX_EN
From DUT
I2C port
To SFP
sites
IRQ_FAN_B
IRQ_QSFP_B
IRQ_RTC_B
PHY_25G_LOL
SI5341_LOL_B
QSFP_MOD_PRS_B
QSFP_MOD_SEL_B
To DUT
interrupt
inputs
From
interrupt
sources
From
fault or
alert
sources
Figure 30. System controller architecture (continued)
The system controller is implemented in a 256-ball micro-BGA Altera CPLD, EPM2210F256C5N.
The system controller is powered continuously using the 3.3 V and 1.8 V regulators, powered from the ATX PSU +5 V standby
power. This allows it to control all aspects of board bring-up, including initial power sequencing.
2.19.1 System configuration
The system controller uses switches to configure the target system into various modes. Switches are sampled and stored in
BRDCFG and DUTCFG registers. BRDCFG registers are always active, and software may change them to result in immediate
changes to the system configuration. DUTCFG registers are used to control processor configuration pins that are only sampled
during PORESET_B, such as RCW_SRC in DUTCFG0. Changes to DUTCFG registers only take effect on the next reset or
reconfiguration event. The following figure shows the configuration hardware arrangement.
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 51 / 116
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