Appendix A
Revision History
The table below summarizes the revisions to this document.
Table 31. Revision history
Revision Date Topic cross-reference Change description
Rev. 4 07/2020 Added notes throughout the document indicating that the
LX2160A processor does not support EVDD operation at
3.3 V but the LX2160ARDB can enable it
Board features Updated DRR-related features in Table 3
DDR interface Updated DDR4 port characteristics
eSDHC interface Updated Figure 16
USB interface Updated Figure 19 and added a note before the last
paragraph
Qixis Programming Model Changed DIP switch names to switch numbers and fixed
other minor issues
Rev. 3 03/2020 DIP switches
• Updated details related to SW2[4:5], SW2[6],
SW3[1:3], SW3[5:7] in Table 21
• Updated Table 22
System controller Removed signal name, RST_MEM[1:2]_B, from Figure 29
System startup Removed RST_MEM[1:2]_B from list of reset devices in
Table 29
Qixis Programming Model Updated details related to STAT_PRES1, RST_FORCE1,
RST_MASK1, and DUTCFG11 registers
Rev. 2 06/2019 Power supply sequence Updated Figure 7
SerDes interface Updated Table 10 to correct mapping between SerDes
lanes and SATA ports
JTAG port Updated Figure 25 to correct voltage/resistor values and
TDI/TDO signal directions
DIP switches Reformatted Table 22 to improve readability
Multi-status LEDs Updated Table 24
Removed all references to PCIe Gen 4 from the document
Rev. 1 10/2018 eSDHC interface Updated the section to mention recommendations against
a silicon erratum on EVDD
Rev. 0 09/2018 Initial public release
NXP Semiconductors
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 115 / 116
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