Concatenated with the QVER register, it forms the full revision information for the CPLD device. This is typically reported as:
qver = get_pixis( QVER );
minor = get_pixis( MINOR );
printf("FPGA: V%d", qver );
if (minor != 0) {
printf(".%d", minor );
}
Note: setting the MINOR/MINTAG register to 5h before reading is optional, as on every reset 05h is the default.
Note: for harmonization with QDS-supporting code (e.g. uboot), if MINOR is zero, do not print it.
Other information can be obtained by writing the corresponding address and reading the register. Reserved fields are found only
in QDS QTAG but are present for compatibility. Contents are as follows:
MINTAG Definition
Address Range Name Definition
0x00-0x03 TAG not implemented.
0x05-0x06 MINOR Minor build version: u16 value in little-endian order.
0x08-0x0B DATE Date/time stamp: u32 Unix GMT time value in big-endian order.
0x0C RELEASE Released flag: 0=unreleased, non-zero=released.
0x10-0x2F NAME not implemented.
0x30-0x7F reserved reserved
Diagram
Bits
7 6 5 4 3 2 1 0
R
MINOR
W
NONE
05h
Fields
Field Function
7-0
MINOR
Read: Data to read from MINOR/MINTAG.
Write: Address of data to read.
3.9 Control and Status Registers
This block of registers control the operation of Qixis itself (or other operations which do not constitute controlling the board or the
DUT, which are managed with BRDCFG/DUTCFG registers) or monitor the status of various things.
NXP Semiconductors
Qixis Programming Model
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 63 / 116
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