NXP Semiconductors QorIQ LX2160A - Page 24

Aquantia
AQR107
PCIe x4 slot
Gen 1-3
LX2160A
x4
Inphi
CS4223
QSFP+
40G-SR4
40G-CR4
40G-KR4
S
E
R
D
E
S
1
Dual RJ45
USXGMII
2x 10G
Dual cage
SFP+
2x 25G
x4
Aquantia
AQR107
Inphi
IN112525
x2
x2
x4
x2
x2
H,G
0,1
F,E
2,3
D-A
4-7
x4
S
E
R
D
E
S
2
A-D
0-3
SATA 3.0SATA 3.0
E-H
4-7
S
E
R
D
E
S
3
PCIe x8 slot
Gen 1-3
x8
A-H
0-7
Protocol #19
Protocol #5
Protocol #2
40G MAC2
25G MAC5
25G MAC6
10G MAC3
10G MAC4
Figure 11. SerDes architecture
The figure below shows the possible SerDes protocol combinations that can be used on the LX2160ARDB.
LX2160A
Lanes 0/H 1/G 2/F 3/E 4/D 5/C 6/B 7/A
Protocol
19
XFI.3 XFI.4 25GE.5 25GE.6
Clocks
LX2160A
Lanes 0/A 1/B 2/C 3/D 4/E 5/F 6/G 7/H
Protocol
5
SATA.3 SATA.4 SATA.1 SATA.2
Clocks
LX2160A
Lanes 0/A 1/B 2/C 3/D 4/E 5/F 6/G 7/H
Protocol
2
Clocks
SerDes 3 : x8 : BackSide
PCIe.5 x8
100.00 MHz
SerDes 2 : x8 : FrontSide
PCIe.3 x4
100.00 MHz
100.00 MHz
SerDes 1 : x8 : FrontSide
40GE.2
161.1328125 MHz
161.1328125 MHz
161.1328125 MHz
Figure 12. SerDes protocol combinations
The table below shows the LX2160ARDB SerDes assignments.
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 24 / 116