NXP Semiconductors QorIQ LX2160A - Page 22

VREF2
D2_MDQS[0:8]
D2_MDQ[0:63]
D2_MECC[0:7]
D2_MDQS[9:17] / D2_MDM[0:8]
D2_MRAS / MCAS / MWE / MACT
D2_MA[0:13]
D2_MBA[0:1]
D2_MALERT / MAPAR / MBG[0:1]
GVDD
Closest
D2_MCK[2:3]
D2_MCKE[2:3]
D2_MODT[2:3]
D2_MCS[2:3]
LX2160A
DDR4 UDIMM
288-pin sockets
Furthest
GVDD
VTT2
2V5
D2_MCS[0:3]
D2_MCK[0:1]
D2_MCKE[0:1]
D2_MODT[0:1]
VCC_SPD
VDD
VDD
VDD
VPP
ADDR
0x53
RESET_n
ADDR
0x54
I2C1_CH0_2V5
(2.5 V I/O shifted)
D2_RST_B
D2_MDIC0
Figure 10. DDR#2 memory port architecture
The following are the characteristics of the DDR4 ports available on the LX2160ARDB:
• Each DDR4 port provides two DIMM connectors (DIMM#1 and DIMM#2), each supporting an industry-standard, 288-pin,
JEDEC-compliant DDR4 UDIMM or RDIMM module with 8-/16-bit data width:
— DDR#1 port DIMM#1 connector (J14) / DDR#2 port DIMM#1 connector (J17) supports four chip selects
(D1_MCS_B[0:3] / D2_MCS_B[0:3]) for single-, dual-, and quad-rank DDR4 memory modules
Quad rank is only supported if the second DIMM connector of a DDR4 port is left unused.
NOTE
— DDR#1 port DIMM#2 connector (J15) / DDR#2 port DIMM#2 connector (J16) supports two chip selects
(D1_MCS_B[2:3] / D2_MCS_B[2:3]) for single- and dual-rank DDR4 memory modules
• Operates at up to 3.2 GigaTransfers/second (GT/s)
• Supports 64-bit data bus
• Supports double-bit error detection and single-bit error correction ECC (8-bit check word across 64-bit data)
• Supports only DDR4 memory
• Supports 4-bit memory devices with minor board modification to remove pull-down resistors that are mounted on the D1 or
D2 MDQS[9:17]_N traces
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 22 / 116