VREF1
VCC_SPD
D1_MDQS[0:8]
D1_MDQ[0:63]
D1_MECC[0:7]
D1_MDQS[9:17] / D1_MDM[0:8]
D1_MRAS / MCAS / MWE / MACT
D1_MA[0:13]
D1_MBA[0:1]
VDD
D1_MALERT / MAPAR / MBG[0:1]
D1_RST_B
D1_MDIC
GVDD
ADDR
0x51
Closest
D1_MCK[2:3]
D1_MCKE[2:3]
D1_MODT[2:3]
D1_MCS[2:3]
LX2160A
RESET_n
DDR4 UDIMM
288-pin sockets
Furthest
GVDD
VTT1
2V5
ADDR
0x52
I2C1_CH0_2V5
(2.5 V I/O shifted)
D1_MCS[0:3]
D1_MCK[0:1]
D1_MCKE[0:1]
D1_MODT[0:1]
VDD
VDD
VPP
Figure 9. DDR#1 memory port architecture
The figure below shows the architecture of the DDR#2 memory port.
NXP Semiconductors
LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 21 / 116