Panasonic FP0 - Page 308

14-66
Num-
ber
Name Boolean Operand Description Steps
F23
P23
32-bit data
addition
D+
PD+
S1, S2, D (S1+1, S1)+(S2+1, S2)→(D+1, D) 11
F25
P25
16-bit data
subtraction
-
P-
S, D (D)-(S)→(D) 5
F26
P26
32-bit data
subtraction
D-
PD-
S, D (D+1, D)-(S+1, S)→(D+1, D) 7
F27
P27
16-bit data
subraction
-
P-
S1, S2, D (S1)-(S2)→(D) 7
F28
P28
32-bit data
subtraction
D-
PD-
S1, S2, D (S1+1, S1)-(S2+1, S2)→(D+1, D) 11
F30
P30
16-bit data
multiplication
*
P*
S1, S2, D (S1)X(S2)→(D+1, D) 7
F31
P31
32-bit data
multiplication
D*
PD*
S1, S2, D (S1+1, S1)X(S2+1, S2)→(D+3, D+2, D+1, D) 11
F32
P32
16-bit data
division
%
P%
S1, S2, D (S1)÷(S2)→quotient (D)
remainder (DT9015 for FP0/FP-e/FP1/FP-M/FP3 or
DT90015 for FP0 T32/FPΣ/FP2/FP2SH/FP10SH)
7
F33
P33
32-bit data
division
D%
PD%
S1, S2, D (S1+1, S1)÷(S2+1, S2)→quotient (D+1, D)
remainder (DT9016, DT9015 for FP0/FP-e/FP1/
FP-M/FP3 or DT90016, DT90015 for FP0 T32/
FPΣ/FP2/FP2SH/FP10SH)
11
F34
P34
16-bit data
multiplication
(result in 16
bits)
*W
P*W
S1, S2, D (S1)X(S2)→(D) 7
F35
P35
16-bit data
increment
+1
P+1
D (D)+1→(D) 3
F36
P36
32-bit data
increment
D+1
PD+1
D (D+1, D)+1→(D+1, D) 3