Panasonic FP0 - Page 322

14-80
Num-
ber
Name Boolean Operand Description Steps
F99
P99
Data table
shift-in and
compress
CMPW
PCMPW
S, D1, D2 Transfer “S” to “D1”. Any parts of the data between
“D1” and “D2” that are 0 are compressed, and
shifted in order toward “D2”.
7
F100
P100
Right shift of
multiple bits
(n bits) in a
16-bit data
SHR
PSHR
D, n Shifts the “n” bits of “D” to the right. 5
F101
P101
Left shift of
multiple bits
(n bits) in a
16-bit data
SHL
PSHL
D, n Shifts the “n” bits of “D” to the left. 5
F102
P102
Right shift of
n bits in a 32-
bit data
DSHR
PDSHR
D, n Shifts the “n” bits of the 32-bit data area specified
by (D+1, D) to the right.
5
F103
P103
Left shift of n
bits in a 32-
bit data
DSHL
PDSHL
D, n Shifts the “n” bits of the 32-bit data area specified
by (D+1, D) to the left.
5
F105
P105
Right shift of
one hexade-
cimal digit
(4-bit)
BSR
PBSR
D Shifts the one digit of data of “D” to the right. 3
F106
P106
Left shift of
one hexade-
cimal digit
(4-bit)
BSL
PBSL
D Shifts the one digit of data of “D” to the left. 3
F108
P108
Right shift of
multiple bits
(n bits)
BITR
PBITR
D1, D2, n Shifts the “n” bits of data range by “D1” and “D2” to
the right.
7
F109
P109
Left shift of
multiple bits
(n bits)
BITL
PBITL
D1, D2, n Shifts the “n” bits of data range by “D1” and “D2” to
the left.
7
F110
P110
Right shift of
one word
(16-bit)
WSHR
PWSHR
D1, D2 Shifts the one word of the areas by “D1” and “D2”
to the right.
5
F111
P111
Left shift of
one word
(16-bit)
WSHL
PWSHL
D1, D2 Shifts the one word of the areas by “D1” and “D2”
to the left.
5
F112
P112
Right shift of
one hexade-
cimal digit
(4-bit)
WBSR
PWBSR
D1, D2 Shifts the one digit of the areas by “D1” and “D2” to
the right.
5