590 Series DC Digital Drive Programming
D-109
SPEED LOOP
Parameter Tag Range
SPEED FBK SELECT 47 See below
Determines the source of the speed feedback signal. The default, ARM VOLTS FBK, uses internal circuitry to derive the speed feedback. The other
selections require the appropriate external device to provide the feedback signal.
0 : ARM VOLTS FBK
1 : ANALOG TACH
2 : ENCODER
3 : ENCODER/ANALOG - for Parker SSD Drives use
Functional Description
Speed Loop PI with Current Demand Isolate
The speed loop output is still valid (active) with the I DMD. ISOLATE parameter enabled.
NOTE
1 The speed loop is reset by unquenching the speed loop/current loop.
2 I DMD. ISOLATE is overridden by Program Stop (B8) or Normal Stop (C3).
3 The speed loop PI holds the integral term as soon as the PI output reaches current limit. This is true even in Current Demand Isolate
mode where it may interfere depending on the way the speed PI is used.
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