RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1107
Dec 10, 2015
17.2 Register Descriptions
Table 17-3 lists the LIN/UART module-related registers.
Table 17-3. List of LIN/UART Module-Related Registers
Register Name Symbol LIN Maste
LIN Slave UART
Peripheral enable register 2 PER2
Input switch control registe
ISC
LIN channel select registe
LCHSEL
LIN clock select registe
LINCKSEL
External interrupt rising edge enable registers 0, 1 EGP0, EGP1
External interrupt falling edge enable registers 0, 1 EGN0, EGN1
LIN wake-up baud rate select registe
LWBR0/LWBR1
LIN/UART baud rate prescaler registe
s LBRP0/LBRP1 —
LIN/UART baud rate prescaler 0 registe
LBRP00/LBRP10
LIN/UART baud rate prescaler 1 registe
LBRP01/LBRP11
LIN self-test control registe
LSTC0/LSTC1
—
UART standby control registe
LUSC0/LUSC1 — —
LIN/UART mode registe
LMD0/LMD1
LIN break field configuration registe
/
UART configuration registe
LBFC0/LBFC1
LIN/UART space configuration registe
LSC0/LSC1
LIN wake-up configuration registe
LWUP0/LWUP1
—
LIN interrupt enable registe
LIE0/LIE1
—
LIN/UART error detection enable registe
LEDE0/LEDE1
LIN/UART control registe
LCUC0/LCUC1
LIN/UART transmission control registe
LTRC0/LTRC1
LIN/UART mode status registe
LMST0/LMST1
LIN/UART status registe
LST0/LST1
LIN/UART error status registe
LEST0/LEST1
LIN/UART data field configuration registe
LDFC0/LDFC1
LIN/UART ID buffer registe
LIDB0/LIDB1
LIN checksum buffer registe
LCBR0/LCBR1
—
UART data buffer 0 registe
LUDB00/LUDB10 — —
LIN/UART data buffer 1 registe
LDB01/LDB11
LIN/UART data buffer 2 registe
LDB02/LDB12
LIN/UART data buffer 3 registe
LDB03/LDB13
LIN/UART data buffer 4 registe
LDB04/LDB14
LIN/UART data buffer 5 registe
LDB05/LDB15
LIN/UART data buffer 6 registe
LDB06/LDB16
LIN/UART data buffer 7 registe
LDB07/LDB17
LIN/UART data buffer 8 registe
LDB08/LDB18
UART operation enable registe
LUOER0/LUOER1 — —
UART option register 1 LUOR01/LUOR11 — —
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