RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 441
Dec 10, 2015
6.3.2 Timer clock select register m (TPSm)
The TPSm register is a 16-bit register that is used to select the operation clocks that are supplied to each channel (CKm0,
CKm1, CKm2, and CKm3) from the external prescaler. For unit 0 of the Group A, B, C, and D products, the clock frequency
of CK00 is selected by using bits 3 to 0 of the TPS0 register, that of CK01 is selected by using bits 7 to 4, that of CK02 is
selected by using bits 11 to 8, and that of CK03 is selected by using bits 15 to 12.
For unit 1 of the Group B, C, and D products, the clock frequency of CK10 is selected by using bits 3 to 0 of the TPS1
register, that of CK11 is selected by using bits 7 to 4, that of CK12 is selected by using bits 9 and 8, and that of CK13 is
selected by using bits 13 and 12.
For the Group E products, the clock frequency of CKm0 is selected by using bits 3 to 0 of the TPSm register, that of
CKm1 is selected by using bits 7 to 4, that of CKm2 is selected by using bits 11 to 8, and that of CKm3 is selected by using
bits 15 to 12.
Rewriting of the TPSm register during timer operation is possible only in the following cases.
If the PRSm00 to PRSm03 bits can be rewritten (n = 0 to 7):
All channels for which CKm0 is selected as the operation clock (CKSmn1, CKSmn0 = 0, 0) are stopped (TEmn = 0).
If the PRSm10 to PRSm13 bits can be rewritten (n = 0 to 7):
All channels for which CKm1 is selected as the operation clock (CKSmn1, CKSmn0 = 1, 0) are stopped (TEmn = 0).
If the PRSm20 to PRSm23 bits can be rewritten (n = 0 to 7):
All channels for which CKm2 is selected as the operation clock (CKSmn1, CKSmn0 = 0, 1) are stopped (TEmn = 0).
If the PRSm30 to PRSm33 bits can be rewritten (n = 0 to 7):
All channels for which CKm3 is selected as the operation clock (CKSmn1, CKSmn0 = 1, 1) are stopped (TEmn = 0).
The TPSm register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
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