RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only)
R01UH0368EJ0210 Rev.2.10 778
Dec 10, 2015
14.2 Registers to Control the Comparator
The comparator is controlled by using the following registers.
Table 14-3. Registers to Control the Comparator
Register Name Symbol After Reset Address Access Size
Peripheral Enable Register 1 PER1 00H F02C0H 8
Comparator Control Register CMPCTL 00H F02A0H 1, 8
Comparator I/O Select Register CMPSEL 00H F02A1H 1, 8
Comparator Output Monitor Register CMPMON 00H F02A3H 1, 8
A/D port configuration register ADPC 00H F0076H 8
D/A converter mode register 2 DAM2 00H F0227H 1, 8
Port mode register 4 PM4 FFH FFF24H 1, 8
Port mode register PM8 FFH FFF28H 1, 8
14.2.1 Peripheral Enable Register 1 (PER1)
The PER1 register enables or disables clock supply to each peripheral hardware unit. Clock supply to a hardware unit
that is not used is stopped in order to reduce the power consumption and noise.
When the comparator is used, be sure to set bit 5 (CMPEN) of this register to 1.
The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 14-2. Format of Peripheral Enable Register 1 (PER1)
Address: F007AH After reset: 00H
Symbol <7> <6> <5> <4> <3> 2 1 <0>
PER1
DACEN
Note
TRGEN
CMPEN
Note
TRD0EN DTCEN 0 0 TRJ0EN
Note Only for the RL78/F14.
Cautions 1. When setting the comparator, be sure to set the CMPEN bit to 1 first. If CMPEN = 0,
writing to a control register of the comparator is ignored, and all read values are default
values (except for port mode registers 4 and 8 (PM4 and PM8), and port registers 4 and
8 (P4 and P8)).
2. Be sure to clear the following bits to 0.
RL78/F13: bits 1, 2, 5, 6, and 7
RL78/F14: bits 1, 2, and 6
CMPEN
Note
Control of comparator input clock R/W
0 Stops input clock supply.
• SFR used by the comparator cannot be written to.
• The comparator is in the reset state.
R/W
1
Supplies input clock.
• SFR used by the comparator can be read/written to.
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