RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 146
Dec 10, 2015
3.2.4 Special function registers (SFRs)
Unlike a general-purpose register, each SFR has a special function.
SFRs are allocated to the FFF00H to FFFFFH area.
SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The
manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Table 3-5 gives a list of the SFRs. The meanings of items in the table are as follows.
Symbol
This item indicates the address of a special function register. It is a reserved word in the assembler, and is defined
as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator,
symbols can be written as an instruction operand.
R/W
This item indicates whether the corresponding SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
Manipulable bit units
“” indicates the manipulable bit unit (1, 8, or 16). “” indicates a bit unit for which manipulation is not possible.
After reset
This item indicates each register status upon reset signal generation.
Caution Do not access addresses to which SFRs are not assigned.
Remark For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs: 2nd Special
Function Registers).
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