RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 810
Dec 10, 2015
15.3.5 Higher 7 bits of the serial data register mn (SDRmn)
The SDRmn register is the transmit/receive data register (16 bits) of channel n.
If operation is stopped (SEmn = 0), bits 15 to 9 are used as a register that sets the division ratio of the operation
clock (f
MCK). If operation is in progress (SEmn = 1), the SDRmn register functions as a transmit/receive buffer register.
If the CCSmn bit of the serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock
by the higher 7 bits of the SDRmn register is used as the transfer clock.
For the function of the SDR register when operation is in progress, see 15.2 Configuration of Serial Array Unit.
SDRmn can be read or written in 16-bit units.
Reset signal generation clears the SDRmn register to 0000H.
Figure 15-8. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H R/W
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0 0 0 0 0 0 0 0 0
SDRmn[15:9] Transfer clock set by dividing the operating clock (fMCK)
0 0 0 0 0 0 0 fMCK/2
0 0 0 0 0 0 1 fMCK/4
0 0 0 0 0 1 0 fMCK/6
0 0 0 0 0 1 1 fMCK/8
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1 1 1 1 1 1 0 fMCK/254
1 1 1 1 1 1 1 fMCK/256
(Cautions and Remarks are listed on the next page.)
FFF11H (SDR00)
FFF10H (SDR00)
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