RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 385
Dec 10, 2015
5.3.7 Operation Speed Mode Control Register (OSMC)
This register is used to reduce power consumption by stopping unnecessary clock functions.
If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions is
stopped in STOP mode or HALT mode while subsystem/low-speed on-chip oscillator select clock is selected as CPU
clock.
Set the OSMC register by an 8-bit memory manipulation instruction.
Writing to the OSMC register is disabled when the GCSC bit of the IAWCTL register is set to 1.
Reset signal generation clears this register to 00H.
Figure 5-14. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
OSMC RTCLPC 0 0
WUTMMCK0
Note
0 0 0 0
RTCLPC
Setting in STOP mode or HALT mode while subsystem/low-speed on-chip oscillator select
clock is selected as CPU clock
0
Enables supply of subsystem/low-speed on-chip oscillator select clock to peripheral
functions
(See Table 23-1 for peripheral functions whose operations are enabled.)
1 Stops supply of subsystem/low-speed on-chip oscillator select clock to peripheral functions
WUTMMCK0
Note
Low-speed on-chip oscillator operation control
0
Low-speed on-chip oscillator stopped
1
Low-speed on-chip oscillator operating
Note To stop the low-speed on-chip oscillator, set bit 4 (WUTMMCK0) to 0 and bit 1 (SELLOSC) of
the clock select register (CKSEL) to 0.
Caution The STOP mode current or HALT mode current when the subsystem/low-speed
on-chip oscillator select clock is used can be reduced by setting the RTCLPC bit
to 1. However, no clock can be supplied to the peripheral functions during HALT
mode while subsystem/low-speed on-chip oscillator select clock is selected as
CPU clock. Set bit 7 (RTCEN) of peripheral enable registers 0 (PER0) to 1 and
bits 0 to 6 of the PER0 register to 0 before setting HALT mode while the
subsystem/low-speed on-chip oscillator clock is selected as CPU clock.
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