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Renesas RL78/D1A User Manual

Renesas RL78/D1A
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RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 813
Dec 10, 2015
15.3.7 Serial status register mn (SSRmn)
The SSRmn register is a register that indicates the communication status and error occurrence status of channel n.
The errors indicated by this register are a framing error, parity error, and overrun error.
The SSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSRmn register can be read with an 8-bit memory manipulation instruction with SSRmnL.
Reset signal generation clears the SSRmn register to 0000H.
Figure 15-10. Format of Serial Status Register mn (SSRmn) (1/2)
Address: F0100H, F0101H (SSR00), F0102H, F0103H (SSR01), After reset: 0000H R
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRmn 0 0 0 0 0 0 0 0 0
TSF
mn
BFF
mn
0 0
FEF
mn
PEF
mn
OVF
mn
TSF
mn
Communication status indication flag of channel n
0 Communication is stopped or suspended.
1 Communication is in progress.
<Clear conditions>
• The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is
set to 1 (communication is suspended).
• Communication ends.
<Set condition>
• Communication starts.
BFF
mn
Buffer register status indication flag of channel n
0 Valid data is not stored in the SDRmn register.
1 Valid data is stored in the SDRmn register.
<Clear conditions>
• Transferring transmit data from the SDRmn register to the shift register ends during transmission.
• Reading receive data from the SDRmn register ends during reception.
• The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is set
to 1 (communication is enabled).
<Set conditions>
• Transmit data is written to the SDRmn register while the TXEmn bit of the SCRmn register is set to 1
(transmission or transmission and reception mode in each communication mode).
• Receive data is stored in the SDRmn register while the RXEmn bit of the SCRmn register is set to 1 (reception or
transmission and reception mode in each communication mode).
• A reception error occurs.
Caution If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the
register is discarded and an overrun error (OVEmn = 1) is detected.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)

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Renesas RL78/D1A Specifications

General IconGeneral
BrandRenesas
ModelRL78/D1A
CategoryComputer Hardware
LanguageEnglish

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