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RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT

R01UH0368EJ0210 Rev.2.10 450

Dec 10, 2015

6.3.4 Timer status register mn (TSRmn)

The TSRmn register indicates the overflow status of the counter of channel n.

The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode

(MDmn3 to MDmn1 = 110B). See Table 6-5 for the operation of the OVF bit in each operation mode and set/clear conditions.

The TSRmn register can be read by a 16-bit memory manipulation instruction.

The lower 8 bits of the TSRmn register can be set with an 8-bit memory manipulation instruction with TSRmnL.

Reset signal generation clears this register to 0000H.

Figure 6-14. Format of Timer Status Register mn (TSRmn)

Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07), After reset: 0000H R

F01E0H, F01E1H (TSR10) to F01EEH, F01EFH (TSR17)

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TSRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF

OVF Counter overflow status of channel n

0 Overflow does not occur.

1 Overflow occurs.

When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.

Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)

2. TSR1n is not provided in the Group A products.

3. TSR17 to TSR14 are not provided in the Group B, C, and D products.

Table 6-5. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode

Timer operation mode OVF bit Set/clear conditions

 Capture mode

 Capture & one-count mode

clear When no overflow has occurred upon capturing

set When an overflow has occurred upon capturing

 Interval timer mode

 Event counter mode

 One-count mode

clear



(Use prohibited)

set

Remark The OVF bit does not change immediately after the counter has overflowed, but changes upon the

subsequent capture.

Renesas RL78/D1A User Manual

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