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RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT

R01UH0368EJ0210 Rev.2.10 439

Dec 10, 2015

6.3 Registers Controlling Timer Array Unit

Timer array unit is controlled by the following registers.

 Peripheral enable register 0 (PER0)

 Timer clock select register m (TPSm)

 Timer mode register mn (TMRmn)

 Timer status register mn (TSRmn)

 Timer channel enable status register m (TEm)

 Timer channel start register m (TSm)

 Timer channel stop register m (TTm)

 Timer input select register 0 (TIS0)

 Timer input select register 1 (TIS1)

 Timer input select register 2 (TIS2)

 Timer output enable register m (TOEm)

 Timer output register m (TOm)

 Timer output level register m (TOLm)

 Timer output mode register m (TOMm)

 PWM output delay control register 1 (PWMDLY1)

 PWM output delay control register 2 (PWMDLY2)

Note 2

 Noise filter enable registers 1, 2 (NFEN1, NFEN2)

 Port mode register (PMxx)

Note 1

 Port register (Pxx)

Note 1

Notes 1. The port mode registers (PMxx) and port registers (Pxx) to be set differ depending on the product. For details,

see 6.3.16 Port mode registers 1, 3, 4, 7, 12 (PM1, PM3, PM4, PM7, PM12).

2. Bit allocation differs depending on the number of pins.

Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)

2. Unit 1 (m = 1) is not provided in the Group A products.

3. Channel numbers 7 to 4 (n = 7 to 4) of unit 1 are not provided in the Group B, C, and D products.

Renesas RL78/D1A User Manual

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