Renesas RL78/D1A User Manual

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 436
Dec 10, 2015
Figure 6-6. Internal Block Diagram of Channel of Timer Array Unit 0
Remark n = 5, 7
6.2.1 Timer count register mn (TCRmn)
The TCRmn register is a 16-bit read-only register and is used to count clocks.
The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
Whether the counter is incremented or decremented depends on the operation mode that is selected by the MDmn3
to MDmn0 bits of timer mode register mn (TMRmn) (refer to 6.3.3 Timer mode register mn (TMRmn)).
Figure 6-7. Format of Timer Count Register mn (TCRmn)
Address: F0180H, F0181H (TCR00) to F018EH, F018FH (TCR07), After reset: FFFFH R
F01C0H, F01C1H (TCR10) to F01CEH, F01CFH (TCR17)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRmn
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
TO0n
PMxx
CKS0n
CCS0n STS0n
2
STS0n
1
STS0n0
MD0n2CIS0n1 CIS0n0
MD0n3
MD0n1
MD0n0
OVF
0n
INTTM0n
f MCK
f
TCLK
TI0n
CK00
CK01
CK02
CK03
Operating
clock selection
Edge
detection
Channel n
Slave channel
Trigger signal from master channel
Clock signal from master channel
Interrupt signal from master channel
Count clock
selection
Trigger
selection
Slave/mater
controller
Timer mode register 0n (TMR0n)
Timer data register 0n (TDR0n)
Timer counter register 0n (TCR0n)
Timer controller
Mode
selection
Output
controller
Interrupt
controller
Output latch
(Pxx)
(Timer interrupt)
Timer status
register 0n (TSR0n)
Overflow
Slave/mater
controller
F0181H (TCR00)
F0180H (TCR00)

Renesas RL78/D1A Specifications

General

Brand	Renesas
Model	RL78/D1A
Category	Computer Hardware
Language	English