Renesas RL78/D1A User Manual

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 435
Dec 10, 2015
Figure 6-4. Internal Block Diagram of Channel of Timer Array Unit 0
Remark n = 0, 2, 4, 6
Figure 6-5. Internal Block Diagram of Channel of Timer Array Unit 0
Remark n = 1, 3
PMxx
CKS0n
CCS0n
MAS
TER0n
STS0n2
STS0n1
STS0n0
MD0n2CIS0n1CIS0n0
MD0n3
MD0n1
MD0n0
OVF
0n
CK03
CK02
f MCK
f TCLK
Interrupt
controller
Output
controller
Output latch
(Pxx)
INTTM0n
(Timer interrupt)
TO0n
Timer status
register 0n (TSR0n)
Overflow
Timer data register 0n (TDR0n)
Timer counter register 0n (TCR0n)
Timer mode register 0n (TMR0n)
Channel n
Timer controller
Trigger
selection
Count clock
selection
Mode
selection
Slave/master
controller
Slave/master
controller
Edge
detection
Operating
clock selection
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
TI0n
CK01
CK00
Master channel
CIS0n1 CIS0n0 MD0n3 MD0n1 MD0n0
T
O0n
PMxx
CKS0n CCS0n
SPLIT
0n
STS0n
2STS0n12n0DM0n0STS
OVF
0n
INTTM0n
CK00
CK01
f MCK
f
TCLK
CK02
CK03
INTTM0nH
TI0n
Slave/mater
controller
Operating
clock selection
Edge
selection
Count clock
selection
Trigger
selection
Trigger signal from master channel
Clock signal from master channel
Interrupt signal from master channel
Timer controller
Mode
selection
Timer counter register 0n (TCR0n)
Timer data register 0n (TDR0n)
8-bit timer
controller
Output
controller
Interrupt
controller
Output latch
(Pxx)
Timer status
register 0n (TSR0n)
Overflow
(Timer interrupt)
(Timer interrupt)
Timer mode register 0n (TMR0n)
Channel n
Slave/mater
controller
Slave channel
Interrupt
controller
Mode
selection

Renesas RL78/D1A Specifications

General

Brand	Renesas
Model	RL78/D1A
Category	Computer Hardware
Language	English