Renesas RL78/D1A User Manual

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 442
Dec 10, 2015
Figure 6-11. Format of Timer Clock Select Register m (TPSm) (8-ch version)
Address: F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPSm
PRS
m33
PRS
m32
PRS
m31
PRS
m30
PRS
m23
PRS
m22
PRS
m21
PRS
m20
PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
PRS
mk3
PRS
mk2
PRS
mk1
PRS
mk0
Selection of operation clock (CKmk)
Note
(k = 0 to 3)
fCLK = 2 MHz fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 32 MHz
0 0 0 0 fCLK 2 MHz 5 MHz 10 MHz 20 MHz 32 MHz
0 0 0 1 fCLK/2 1 MHz 2.5 MHz 5 MHz 10 MHz 16 MHz
0 0 1 0 fCLK/2
2
500 kHz 1.25 MHz 2.5 MHz 5 MHz 8 MHz
0 0 1 1 fCLK/2
3
250 kHz 625 kHz 1.25 MHz 2.5 MHz 4 MHz
0 1 0 0 fCLK/2
4
125 kHz 312.5 kHz 625 kHz 1.25 MHz 2 MHz
0 1 0 1 fCLK/2
5
62.5 kHz 156.2 kHz 312.5 kHz 625 kHz 1 MHz
0 1 1 0 fCLK/2
6
31.25 kHz 78.1 kHz 156.2 kHz 312.5 kHz 500 kHz
0 1 1 1 fCLK/2
7
15.62 kHz 39.1 kHz 78.1 kHz 156.2 kHz 250 kHz
1 0 0 0 fCLK/2
8
7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz 125 kHz
1 0 0 1 fCLK/2
9
3.91 kHz 9.76 kHz 19.5 kHz 39.1 kHz 62.5 kHz
1 0 1 0 fCLK/2
10
1.95 kHz 4.88 kHz 9.76 kHz 19.5 kHz 31.25 kHz
1 0 1 1 fCLK/2
11
976 Hz 2.44 kHz 4.88 kHz 9.76 kHz 15.63 kHz
1 1 0 0 fCLK/2
12
488 Hz 1.22 kHz 2.44 kHz 4.88 kHz 7.81 kHz
1 1 0 1 fCLK/2
13
244 Hz 610 Hz 1.22 kHz 2.44 kHz 3.91 kHz
1 1 1 0 fCLK/2
14
122 Hz 305 Hz 610 Hz 1.22 kHz 1.95 kHz
1 1 1 1 fCLK/2
15
61 Hz 153 Hz 305 Hz 610 Hz 976 Hz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), stop timer
array unit (TTm = 00FFH).
Cautions 1. TPS1 is not provided in the Group A products, because the timer array unit 1 is not provided.
This format cannot be applied to unit 1 of the Group B, C, and D products (see the specifications
of 4-channel version in Figure 6-12).
2. When selecting f
CLK (not divided) as the operation clock (CKmk) and setting TDRnm = 0000H (n =
0, 1; m = 0 to 7), set the interrupt mask flag to “interrupt processing disabled” (TMMKnm = 1).
Remarks 1. f
CLK: CPU/peripheral hardware clock frequency
2. The above clock becomes high level for one period of f
CLK from its rising edge (m = 0, 1). For details, see
6.5.1 Count clock (f
TCLK).

Renesas RL78/D1A Specifications

General

Brand	Renesas
Model	RL78/D1A
Category	Computer Hardware
Language	English