RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 378
Dec 10, 2015
Figure 5-7. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H After reset: 07H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection
fX = 10 MHz fX = 20 MHz
0 0 0 2
8
/fX 25.6
s 12.8
s
0 0 1 2
9
/fX 51.2
s 25.6
s
0 1 0 2
10
/fX 102.4
s 51.2
s
0 1 1 2
11
/fX 204.8
s 102.4
s
1 0 0 2
13
/fX 819.2
s 409.6
s
1 0 1 2
15
/fX 3.27 ms 1.63 ms
1 1 0 2
17
/fX 13.10 ms 6.55 ms
1 1 1 2
18
/fX 26.21 ms 13.10 ms
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
register before executing the STOP instruction.
2. Change the setting of the OSTS register before setting the MSTOP bit of the clock
operation status control register (CSC) to 0.
3. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
4. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by the OSTS register.
In the following cases, set the oscillation stabilization time of the OSTS register to
the value equal to or greater than the count value which is to be checked by the
OSTC register after the oscillation starts.
If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or
subsystem clock is being used as the CPU clock.
If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note,
therefore, that only the status up to the oscillation stabilization time set by the
OSTS register is set to the OSTC register after the STOP mode is released.)
5. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
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