RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 525
Dec 10, 2015
Figure 6-71. Operation Procedure of One-Shot Pulse Output Function (2/2)
Software Operation Hardware Status
Operation
start
Sets the TOEmp bit (slave) to 1 (only when operation is
resumed).
The TSmn (master) and TSmp (slave) bits of timer
channel start register m (TSm) are set to 1 at the same
time.
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
The TEmn and TEmp bits are set to 1 and the master
channel enters the TImn input edge detection wait status.
Counter stops operating.
Detects the TImn pin input valid edge of master channel. Master channel starts counting.
During
operation
Set values of only the CISmn1 and CISmn0 bits of the
TMRmn register can be changed.
Sets corresponding bit of noise filter enable registers 1
and 2 (NFEN1 and NFEN2) to 1.
Set values of the TMRmp, TDRmn, TDRmp registers,
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be
changed.
The TCRmn and TCRmp registers can always be read.
The TSRmn and TSRmp registers are not used.
Set values of the TOm and TOEm registers of slave
channel can be changed.
Master channel loads the value of the TDRmn register to
timer count register mn (TCRmn) when the TImn pin valid
input edge is detected, and the counter starts counting
down. When the count value reaches TCRmn = 0000H,
the INTTMmn output is generated, and the counter stops
until the next valid edge is input to the TImn pin.
The slave channel, triggered by INTTMmn of the master
channel, loads the value of the TDRmp register to the
TCRmp register, and the counter starts counting down.
The output level of TOmp becomes active one count clock
after generation of INTTMmn from the master channel. It
becomes inactive when TCRmp = 0000H, and the
counting operation is stopped.
After that, the above operation is repeated.
Operation
stop
The TTmn (master) and TTmp (slave) bits are set to 1 at
the same time.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
TEmn, TEmp = 0, and count operation stops.
The TCRmn and TCRmp registers hold count value and
stop.
The TOmp output is not initialized but holds current
status.
The TOEmp bit of slave channel is cleared to 0 and
value is set to the TOmp bit.
The TOmp pin outputs the TOmp set level.
TAU
stop
To hold the TOmp pin output level
Clears the TOmp bit to 0 after the value to
be held is set to the port register.
When holding the TOmp pin output level is not
necessary
Setting not required.
The TOmp pin output level is held by port function.
The TAUmEN bit of the PER0 register is cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set to
port mode.)
Remarks 1. m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
2. Unit 1 is not provided in the Group A products.
Channels 7 to 4 of unit 1 are not provided in the Group B, C, and D products.
Operation is resumed.
To Next Page
Loading...
Need help?
General
