RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 806
Dec 10, 2015
Figure 15-6. Format of Serial Mode Register mn (SMRmn) (2/2)
Address: F0108H, F0109H (SMR00), F010AH, F010BH (SMR01), After reset: 0020H R/W
F0148H, F0149H (SMR10), F014AH, F014BH (SMR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn
CKS
mn
CCS
mn
0 0 0 0 0
STS
mn
0
SIS
mn0
1 0 0
MD
mn2
MD
mn1
MD
mn0
SIS
mn0
Controls inversion of level of receive data of channel n in UART mode
0
Falling edge is detected as the start bit.
The input communication data is captured as is.
1
Rising edge is detected as the start bit.
The input communication data is inverted and captured.
MD
mn2
MD
mn1
Setting of operation mode of channel n
0 0 CSI mode
0 1 UART mode
1 0 Simplified I
2
C mode
1 1 Setting prohibited
MD
mn0
Selection of interrupt source of channel n
0 Transfer end interrupt
1 Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
For successive transmission, the next transmit data is written by setting the MDmn0 bit to 1 when SDRmn data has
run out.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 to 0. Be sure to set bit 5 to 1.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10, 11),
q: UART number (q = 0, 1), r: IIC number (r = 00, 01, 10, 11)
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