RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 970
Dec 10, 2015
15.7.2 UART reception
UART reception is an operation wherein this MCU asynchronously receives data from another device (start-stop
synchronization).
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the
odd- and even-numbered channels must be set.
UART UART0 UART1
Target channel Channel 1 of SAU0 Channel 1 of SAU1
Pins used RxD0 RxD1
Interrupt INTSR0 INTSR1
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag • Framing error detection flag (FEFmn)
• Parity error detection flag (PEFmn)
• Overrun error detection flag (OVFmn)
Transfer data length 7 to 9 or 16 bits
Transfer rate Max. fMCK/6 [bps] (SDRmn [15:9] = 3 or more), Min. fCLK/(2 × 2
15
× 128) [bps]
Note
Data phase Forward output (default: high level)
Reverse output (default: low level)
Parity bit The following selectable
• No parity bit (no parity check)
• Appending 0 parity (no parity check)
• Appending even parity
• Appending odd parity
Stop bit Appending 1 bit
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications.
Remarks 1. f
MCK: Operation clock frequency of target channel
f
CLK: System clock frequency
2. m: Unit number (m = 0, 1), n: Channel number (n = 1), mn = 01, 11
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