Renesas RL78/F14 - CAN Receive FIFO Control Register M (Rfccm) (M = 0, 1)

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1325
Dec 10, 2015
18.3.34 CAN Receive FIFO Control Register m (RFCCm) (m = 0, 1)
Address RFCC0L: F0338H, RFCC0H: F0339H
RFCC1L: F033AH, RFCC1H: F033BH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
RFIGCV[2:0] RFIM — RFDC[2:0] — — — — — — RFIE RFE
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to
13
RFIGCV[2:0] Receive FIFO Interrupt
Request
Timing Select
b15 b14 b13
0 0 0 : When FIFO is 1/8 full.
0 0 1 : When FIFO is 2/8 full.
0 1 0 : When FIFO is 3/8 full.
0 1 1 : When FIFO is 4/8 full.
1 0 0 : When FIFO is 5/8 full.
1 0 1 : When FIFO is 6/8 full.
1 1 0 : When FIFO is 7/8 full.
1 1 1 : When FIFO is full.
R/W
12 RFIM Receive FIFO Interrupt Source
Select
0: An interrupt occurs when the condition set by the
RFIGCV[2:0] bits is met.
1: An interrupt occurs each time a message has been
received.
R/W
11 — Reserved This bit is always read as 0. The write value should always be
0.
R
10 to 8 RFDC[2:0] Receive FIFO Buffer Depth
Configuration
b10 b9 b8
0 0 0 : 0 messages
0 0 1 : 4 messages
0 1 0 : 8 messages
0 1 1 : 16 messages
1 0 0 : Setting prohibited
1 0 1 : Setting prohibited
1 1 0 : Setting prohibited
1 1 1 : Setting prohibited
R/W
7 to 2 — Reserved These bits are always read as 0. The write value should
always be 0.
R
1 RFIE Receive FIFO Interrupt Enable 0: Receive FIFO interrupt is disabled.
1: Receive FIFO interrupt is enabled.
R/W
0 RFE Receive FIFO Buffer Enable 0: No receive FIFO buffer is used.
1: Receive FIFO buffers are used.
R/W
• RFIGCV[2:0] Bits
These bits are used to specify the fraction of the transmit/receive FIFO buffer (the number of messages is
selected by the setting of the RFDC[2:0] bits) that must be filled for the FIFO buffer to generate a receive
interrupt request when the RFIM bit is set to 0.
When the RFDC[2:0] bits are set to B'001 (4 messages), set the RFIGCV[2:0] bits to B'001, B'011, B'101, or
B'111. Modify these bits only in global reset mode.
• RFIM Bit
This bit is used to select a FIFO interrupt source. Modify this bit only in global reset mode.
• RFDC[2:0] Bits
These bits are used to select the number of messages that can be stored in a single receive FIFO buffer. If
these bits are set to B'000, do not use any receive FIFO buffer. Modify these bits only in global reset mode.