RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1288
Dec 10, 2015
18.3.3 CANi Control Register L (CiCTRL) (i = 0)
Address C0CTRLL: F0304H, C0CTRLH: F0305H
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
ALIE BLIE OLIE BORIE BOEIE EPIE EWIE BEIE — — — — RTBO CSLPR CHMDC
[1:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit Symbol Bit Name Description R/W
15 ALIE Arbitration Lost Interrupt Enable 0: Arbitration lost interrupt is disabled.
1: Arbitration lost interrupt is enabled.
R/W
14 BLIE Bus Lock Interrupt Enable 0: Bus lock interrupt is disabled.
1: Bus lock interrupt is enabled.
R/W
13 OLIE Overload Frame Transmit
Interrupt Enable
0: Overload frame transmit interrupt is disabled.
1: Overload frame transmit interrupt is enabled.
R/W
12 BORIE Bus Off Recovery Interrupt Enable 0: Bus off recovery interrupt is disabled.
1: Bus off recovery interrupt is enabled.
R/W
11 BOEIE Bus Off Entry Interrupt Enable 0: Bus off entry interrupt is disabled.
1: Bus off entry interrupt is enabled.
R/W
10 EPIE Error Passive Interrupt Enable 0: Error passive interrupt is disabled.
1: Error passive interrupt is enabled.
R/W
9 EWIE Error Warning Interrupt Enable 0: Error warning interrupt is disabled.
1: Error warning interrupt is enabled.
R/W
8 BEIE Protocol Error Interrupt Enable 0: Protocol error interrupt is disabled.
1: Protocol error interrupt is enabled.
R/W
7 to 4 — Reserved These bits are always read as 0. The write value should
always be 0.
R
3 RTBO Forcible Return from Bus-off When this bit is set to 1, forcible return from the bus off
state is made. This bit is always read as 0.
R/W
2 CSLPR Channel Stop Mode 0: Other than channel stop mode
1: Channel stop mode
R/W
1, 0 CHMDC
[1:0]
Mode Select
b1 b0
0 0: Channel communication mode
0 1: Channel reset mode
1 0: Channel halt mode
1 1: Setting prohibited
R/W
• ALIE Bit
When the ALF flag in the CiERFLL register is set to 1 with the ALIE bit set to 1, an error interrupt request is
generated. Modify this bit only in channel reset mode.
• BLIE Bit
When the BLF flag in the CiERFLL register is set to 1 with the BLIE bit set to 1, an error interrupt request is
generated. Modify this bit only in channel reset mode.
• OLIE Bit
When the OVLF flag in the CiERFLL register is set to 1 with the OLIE bit set to 1, an error interrupt request is
generated. Modify this bit only in channel reset mode.
• BORIE Bit
When the BORF flag in the CiERFLL register is set to 1 with the BORIE bit set to 1, an error interrupt request is
generated. Modify this bit only in channel reset mode.
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